Principal Engineer, Parallel Computing Lab
Chris Hughes leads a team within the Parallel Computing Lab, focusing on workload-driven processor architecture research, for highly parallel workloads (e.g., HPC, machine learning). Chris joined Intel in 2003, directly into his current lab. He led the teams that defined the AVX2/AVX-512 gather and scatter instructions, and conflict detection instructions (i.e., AVX-512CD). In addition to his work on SIMD ISA, he has led projects on cache optimizations for many-core architectures, as well as core-to-core communication and synchronization. Before joining Intel, Chris was at the University of Illinois at Urbana-Champaign, where he earned his Ph.D. in Computer Science.